Associate Professor at Jaypee Institute of Information Technology, Noida, India
Dr. Satyendra Kumar 👨🏫 is an Associate Professor in the Department of Electronics & Communication Engineering at Jaypee Institute of Information Technology (JIIT), Noida 🇮🇳. With a Ph.D. in low power SRAM design from JIIT 🧠🔋, and both B.Tech and M.Tech degrees from IIT Roorkee 🎓, he brings deep expertise in semiconductor device modeling, VLSI, and memory circuits. He has served in prestigious roles such as Editorial Board Member and Technical Program Committee Member for IEEE-sponsored conferences 🧾🎤. Passionate about innovation in low-power electronics and memory technologies, he actively contributes to research and academic development 💡📘.
Professional Profile:
Scopus
🔹 Education & Experience
🎓 Ph.D. (Electronics & Communication Engineering)
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Jaypee Institute of Information Technology, Noida (2018)
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Thesis: Robust Low Power Low Voltage SRAM Design
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Advisor: Prof. Hariom Gupta
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Co-advisor: Dr. Kaushik Saha
🎓 M.Tech. (Electronics & Communication Engineering)
🎓 B.Tech. (Electronics & Communication Engineering)
👨🏫 Associate Professor
🔹 Professional Development
Dr. Satyendra Kumar continuously engages in professional development through active participation in IEEE-sponsored events 🤝📡. He has served as Co-Track Chair for VLSI Technology & Embedded Systems at ICSC 2022 & 2023 🎙️, and is a long-time Technical Program Committee member for ICSC since 2019 🗓️. As an Editorial Board Member of the Journal of Electrical and Electronic Engineering 📰, he stays at the forefront of current trends and innovations. His involvement in organizing conferences, reviewing research, and collaborating with industry professionals like Samsung R&D 🏢 enables him to stay updated and guide future engineers effectively 👨🔧📚.
🔹 Research Focus
Dr. Satyendra Kumar’s research centers on low-power and high-performance memory design 🧠⚡, particularly SRAM-based solutions for energy-constrained systems such as mobile and embedded devices 📱🔋. He explores advanced read/write assist techniques, low-voltage operation, and robust design for VLSI circuits 🛠️📐. His work also spans modeling and simulation of semiconductor devices, enhancing circuit reliability under process variations 🧪🔍. With a strong emphasis on low power applications, his research contributes significantly to the fields of nanotechnology, embedded systems, and next-generation computing architectures 💻🚀. His commitment to energy-efficient electronics positions him at the cutting edge of semiconductor research 🌱🔬.
🔹 Awards and Honors
🏅 Editorial Board Member, Journal of Electrical and Electronic Engineering (since 2018)
🏅 Co-Track Chair, VLSI Technology & Embedded Systems – ICSC 2022 & 2023 (IEEE Co-sponsored)
🏅 TPC Member, International Conference on Signal Processing and Communication (ICSC) – since 2019
Publication Top Notes
1. Device and circuit-level assessment of temperature variation on the DC, Analog/RF and linearity performance metrics of III-V TFETs for reliability
Authors: P. Verma, Priyanka; S. Kumar, Satyendra
Journal: Micro and Nanostructures, 2025
Overview:
This article investigates how temperature variations affect the performance of III-V Tunnel Field Effect Transistors (TFETs). The study focuses on DC characteristics, analog/RF performance, and linearity—essential for reliable low-power circuit operation. It provides insights into design margins and the robustness of these devices under thermal stress at both device and circuit levels.
2. Negative capacitance double-gate MOSFET for advanced low-power electronic applications
Authors: A.N. Kumar, Amit N.; S. Chaturvedi, Saurabh; S. Kumar, Satyendra
Journal: Microelectronics Journal, 2025
Overview:
This work proposes and analyzes a Negative Capacitance Double-Gate MOSFET structure, leveraging ferroelectric materials to reduce power consumption. The study evaluates key parameters like subthreshold swing and leakage current, indicating significant improvements for future low-power applications.
3. Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si₀.₇Ge₀.₃ Source Region at Device and Circuit Level
Authors: K.S. Singh, Km Sucheta; S. Kumar, Satyendra
Journal: Journal of Circuits, Systems and Computers, 2024
Overview:
This article explores a dual-material gate heterojunction TFET design, particularly focusing on the Si₀.₇Ge₀.₃ source region. It performs a mole fraction-dependent reliability analysis and studies vertical tunneling effects, addressing improvements in device scalability, leakage control, and circuit performance.
Conclusion
Dr. Satyendra Kumar is a strong and suitable candidate for a Best Researcher Award, especially in the domain of VLSI design and semiconductor device research. His work addresses key challenges in low-power design—critical for mobile and embedded systems. His academic credentials, consistent involvement in IEEE conferences, and editorial roles further reflect his dedication and contribution to the scientific community.